1. Field of the Invention
The present invention relates to an interface device, and more particularly, to a NAND flash memory interface device interfacing between a host processor and a NAND flash memory.
2. Description of the Related Art
A flash memory is a non-volatile memory, which enables on-line data programming and deleting. The flash memory electrically deletes the data using a same method as that of an electrically erasable and programmable ROM (EEPROM), and the memory may be entirely deleted in one second or several seconds. The data stored in the flash memory is deleted throughout the chip in a block unit, but it is impossible to delete the data in a byte unit. The flash memory stores a correctable control program, which is used instead of an auxiliary memory.
The flash memory is divided into a NAND flash memory and a NOR type flash memory. The NOR type flash memory uses an interface method as an SRAM or a ROM to easily construct a circuit with a processor. Further, the NAND flash memory is more sophisticated using the interface method than the NOR type flash memory and has an advantage of lower economic costs. However, the NAND flash memory has a higher degree of integration than the NOR flash memory.
FIG. 1 is a block diagram showing a connection of a host processor 10 and a NAND flash memory 30.
The host processor 10 includes a plurality of control wires, a plurality of address signal wires, and a plurality of data signal wires. The NAND flash memory 30 includes a plurality of control wires and an I/O (Data Input/Output) signal wire including 8 bits from I/O 0 to I/O 7.
The control wires of the host processor 10 (i.e., CLE (Command Latch Enable), ALE (Address Latch Enable), CE (Chip Enable), RE (Read Enable), WE (Write Enable) control wires) are connected to corresponding control wires of the NAND flash memory 30. The plurality of address signal wires and the plurality of data signal wires of the host processor 10 are connected with the I/O signal wire of the NAND flash memory 30. An R/B (Ready/Busy output) control wire of the NAND flash memory 30 is connected to a corresponding control wire of the processor 10.
Hereinbelow, the descriptions will be made about the operation of the NAND flash memory 30 in the above-connected state, and, for example, when the data is extracted from the NAND flash memory 30. The host processor 10 sets the signal of the CLE control wire at ‘high’ level and transmits a READ command to the NAND flash memory 30 through the I/O signal wire. After transmitting the READ command, the host processor 10 sets the signal of the ALE control wire at ‘high’ level and transmits an address to the NAND flash memory 30 through the I/O signal wire. The address transmitted from the host processor 10 is an address that is assigned to a location of the NAND flash memory 30 from which the data is extracted. Upon receipt of the READ command and the address, the NAND flash memory 30 extracts the data from an internal memory cell and transmits the extracted data to an internal input/output buffer. At this time, a signal level of the R/B control wire of the NAND flash memory 30 becomes “low”, which means that an inner operation is being performed i.e., in a BUSY state.
When the inner operation of the NAND flash memory 30 is completed, the signal level of the R/B control wire becomes “high” and the data stored in the internal input/output buffer is transmitted to the host processor 10 through the I/O signal wire. The CE, RE, and WE control wires among the control wires, are operated the same as the interfacing method used in a general SRAM.
As set forth above, in order to use the NAND flash memory 30, a circuit is required to operate CLE, ALE, and R/B control wires in addition to the CE, RE, WE control wires that are used in the general SRAM. Also, the command, the address, and the data have to be transmitted through the I/O signal wire between the host processor 10 and the NAND flash memory 30. Thus, the NAND flash memory is not compatible with the general interface method used in the memory.
Conventionally, the ALE, CLE, and R/B control wires are connected to a GPIO port in order to use the NAND flash memory 30. Another method is to connect the CLE and ALE control wires to the 0th address signal wire and the 1st address signal wire of the processor, respectively, and to connect the R/B control wire to one of the upper data wires that are not in use.
However, the above-mentioned methods are rather complicated to control the NAND flash memory and a processing speed of the entire operations is slow. Also, because the I/O signal wire of the NAND flash memory 30 includes 8 bits, at least two NAND flash memories are required when a demanded data width is equal to or more than 16 bits. Accordingly, a number of the NAND flash memory has to increase depending on a type of the processor, and thus, there is a problem of enlarged size of the entire circuit.
Also, there is a problem when the NAND flash memory 30 stores a booting code. With respect to the booting code, when the NAND flash memory 30 supports an error correction code (ECC) checking function in a software-like method without an extra circuit, a booting speed is slow. Accordingly, an extra circuit is required.